The present invention relates to a method for manufacturing a semiconductor elemental device. Thinning of a gate insulating film of a MOS (Metal-Oxide-Semiconductor) transistor has been underway with miniaturization and speeding up of a semiconductor elemental device. In a conventionally-used gate insulating film formed of an oxide film, however, a leakage current begins to flow therein when its thickness reaches 2 nm or less, thus resulting in an increase in power consumption. Therefore, the introduction of a high permittivity material higher in permittivity than a silicon oxide film has been discussed as the gate insulating film in 65-nm generation and later devices.
An oxide film conversion thickness obtained by converting the thickness of a gate insulating film formed of a high permittivity material to an oxide film is defined as the oxide film conversion thickness=(permittivity of oxide film/permittivity of dielectric)×actual thickness as is well known. Since the actual thickness can be increased with a material high in permittivity, the application of the high permittivity material to the gate insulating film is a means effective in suppressing the leakage current.
A conventional method for manufacturing a semiconductor elemental device will be explained with reference to FIG. 4 (refer to, for example, a patent document 1 (Japanese Unexamined Patent Publication No. 2003-332295)).
An SOI substrate having a structure in which an insulating layer 14 and an SOI (Silicon on Insulator) layer 16 are laminated over a support substrate 12 in this order, is first prepared as a semiconductor substrate 10 (see FIG. 4(A)).
Next, device isolation insulating layers 18 are formed in the SOI layer 16 of the semiconductor substrate 10 by a local oxide of silicon (LOCOS) method to perform device isolation with respect to active regions. A substrate in which the device isolation insulating layers 18 are formed in the SOI layer 16 is referred to as a bed or base substrate 11. Incidentally, portions of the active regions in the SOI layer 16 are called active SOI layers 17. Next, a high dielectric film 56 and a polysilicon film 65 are sequentially stacked over the base substrate 11 (see FIG. 4(B)).
Next, photoresist masks 70 are formed on the polysilicon film 65 corresponding to each gate forming region 72 by a photolithography method (see FIG. 4(C)).
Next, dry etching using the photoresist masks 70 is carried out to remove the polysilicon film 65 corresponding to each gate non-forming region 74, thereby constituting the polysilicon film 65 that remains in each gate forming region 72, as a gate electrode 67 (see FIG. 4(D)).
Next, the photoresist masks 70 are removed by ashing. Thereafter, portions of the high dielectric film 56 corresponding to the gate non-forming regions 74 are removed by low-temperature wet etching using hydrofluoric acid as an etchant (see FIG. 4(E)).
When, however, for example, hafnium oxide (HfO2) whose crystallization temperature (ranging from 500 to 600° C.) is lower than a deposition temperature of polysilicon is applied to a gate insulating film as a high permittivity material, a high dielectric film of HfO2 is crystallized upon deposition or growth of polysilicon. When the high dielectric film is crystallized, there is a fear that an etching rate of the high dielectric film is reduced or no etching proceeds.
A method has also been reported wherein even when the high dielectric film is crystallized in contrast to this, a plasma etching process using HBr, CL2 or an O2 gas is performed following dry etching for forming a gate electrode (refer to, for example, T. Maeda et al., Ext. Abstracts, SSDM, p. 828(2003)). According to this method, a crystallized high dielectric film is damaged using an ion impact by the plasma etching process so as to be amorphized, after which its amorphized damage layer is removed by wet etching.
There is however a fear that the HBr, Cl2 or O2 gas used for the formation of the damage layer damages the crystallized high dielectric film and amorphizes the high dielectric film and at the same time etches polysilicon corresponding to the gate electrode.